Technology is continually seeking to miniaturize the individual components within an integrated circuit while concurrently increasing the complexity of the circuitry. Because of these seemingly contrary demands, the art has had to develop innovative methods for positioning and electrically interconnecting the various components which are located on an integrated circuit. One well known solution developed by the art includes forming multilevel interconnections wherein two or more conductors which are on different levels of the integrated circuit are electrically interconnected by means of a via, or through-hole, which has been filled or plated with electrically conductive material. The conductors are separated everywhere else by an intermediate dielectric layer.
Currently, these multilevel conductive interconnects are formed using only a single layer of plasma enhanced deposited silicon nitride as the intermediate dielectric material. This current method is adequate, however there are shortcomings associated with it.
Firstly, the dielectric layer is deposited onto a first conductive strip, which is typically not planar but rather has discrete sides and a top surface. Therefore, the dielectric layer takes on the shape of this underlying first conductive strip, curving around and over the corners of the underlying conductive strip. Thus when the second overlaying conductor is deposited onto the dielectric, the second conductor must also conform to any curves, corners or steps in the dielectric layer. Typically, the second conductor adheres poorly around these corners or steps. This results in high electrical resistance in the conductor at these points, a feature highly undesirable for an electrical conductor.
Another shortcoming associated with this conventional method arises because there is only a single intermediate dielectric layer between the first and second metal conductors. If the dielectric layer has any defects, the defects may result in electrical shorting between the first and second metal conductors. Again, this is highly undesirable in an integrated circuit.
Therefore, it is desirable to provide an electrical interconnection means which alleviates these current shortcomings by providing (1) a planarized surface for deposition of the second metal conductor so as to eliminate the problem of poor step coverage and associated high electrical resistance, and (2) a dual dielectric intermediate layer between the surrounding first and second metal conductors so as to result in noncoincident alignment of defects and alleviate the problem of electrical shorting between the conductors.